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? semiconductor components industries, llc, 2008 december, 2008 ? rev. 0 1 publication order number: ncv8614/d ncv8614 ultra-low iq automotive system power supply ic power saving triple-output linear regulator the ncv8614 is a multiple output linear regulator ic?s with an automatic switchover (aso) input voltage selector. the aso circuit selects between three different input voltage sources to reduce power dissipation and to maintain the output voltage level across varying battery line voltages associated with an automotive environment. the ncv8614 is specifically designed to address automotive radio systems and instrument cluster power supply requirements. the ncv8614 can be used in combination with the 4 ? output controller/regulator ic, ncv885x, to form a complete automotive radio or instrument cluster power solution. the ncv8614 is intended to supply power to various ?always on? loads such as the can transceivers and microcontrollers (core, memory and io). the ncv8614 has three output voltages, a reset / delay circuit, and a host of control features suitable for the automotive radio and instrument cluster systems. features ? operating range 7.0 v to 18.0 v (45 v load dump tolerant) ? output voltage tolerance, all rails, 2% ? < 50 a quiescent current ? independent input for ldo3 linear regulator ? high voltage ignition buffer ? automatic switchover input voltage selector ? independent input voltage monitor with a high input voltage and low input voltage (brown ? out) indicators ? thermal warning indicator with thermal shutdown ? single reset with externally adjustable delay for the 3.3 v rail ? push ? pull outputs for logic level control signals ? all ceramic solution for reduced leakage current at the output ? ncv prefix for automotive and other applications requiring site and control changes ? this is a pb ? free device applications ? automotive radio ? instrument cluster pin connections ordering information marking diagram aso_rail vin ? h vin_s3 vin ? b vin ? a vout1 vbatt_mon vout3fb hv_det bo_det nc gnd hot_flg vout3 vout2 rst dly gnd ignout ignin ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. device package shipping ? NCV8614MNR2G dfn20 (pb ? free) 2500 / tape & reel http://onsemi.com dfn20 mn suffix case 505ab 1 20 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package ncv8614 awlyyww (note: microdot may be in either location)
ncv8614 http://onsemi.com 2 i limit tsd i limit v ref v ref v int v rfb1 v th2 v th1 switchover control circuit i limit v th1 v th2 v pp v pp v pp vin-h vin-a vin-b vbatt ignout ignin bo_det hv_det hot_flg adj voltage vin_s3 3.3 v rst dly gnd vin_mon 12 5 11 10 7 6 4 3 2 13 17 16 18 20 19 v rfb2 v rfb3 vbatt_mon vin_mon 9 hv_det fault logic 8 gnd v out1 v out2 v out3 tsd d1 d3 15 14 v pp 8 nc v out3 fb 5 v ovs aso_rail 1 d2 8 v v ref v out3 fb v rfb3 v bg 1 uf 1000 uf 1 uf v rth v ref v pp rst2 clamp 10 k + 5v components value manufacturer d1 mbrs2h100t3g on semiconductor d2 mbr0502t1 on semiconductor d3 mmdl914t1 on semiconductor figure 1. typical circuit with the internal schematic
ncv8614 http://onsemi.com 3 pin function descriptions pin no. symbol description 1 aso_rail output/input of the automatic switchover (aso) circuitry. place a 1 uf ceramic capacitor on this pin to provide local bypassing to the ldo linear regulator pass devices. 2 vin ? b primary power supply input. connect battery to this pin through a blocking diode. 3 vin ? h holdup power supply rail. connect a storage capacitor to this pin to provide a temporary backup rail during loss of battery supply. a bleed resistor (typically 1 k ) is needed from vin ? b to this pin in order to trickle charge this capacitor. 4 vin ? a voltage monitor which determines whether the 8 v supply is able to power the outputs. if the 8 v supply is present, the fet?s connected to vin ? b and vin ? h will be turned off, and the 8 v supply will be providing power to the outputs. if the 8 v supply is not present, the fet?s on vin ? b and vin ? h will be left on, and the greater of those voltages will be driving the outputs. 5 vbatt_mon vbatt monitor pin. to operate overvoltage shutdown, hv_det and bo_det, connect this pin to aso_rail or battery. to eliminate overvoltage shutdown, hv_det and bo_det, tie this pin to ground. 6 hv_det high ? voltage detect output. when vbatt_mon surpasses 17 v, this pin will be driven to ground. during normal operation, this pin is held at v pp . 7 bo_det brown out indicator output. when vbatt_mon and vin ? a falls below 7.5 v, this pin will be driven to ground. during normal operation, this pin is held at v pp . 8 nc no connect 9 gnd ground. reference point for internal signals. internally connected to pin 13. ground is not con- nected to the exposed pad of the dfn20 package. 10 hot_flg thermal warning indicator. this pin provides an early warning signal of an impending thermal shutdown. 11 ignin ignition buffer input 12 igout ignition buffer logic output 13 gnd ground. reference point for internal signals. internally connected to pin 9. ground is not con- nected to the exposed pad of the dfn20 package. 14 dly delay pin. connect a capacitor to this pin to set the delay time. 15 rst reset pin. monitors v out1. 16 v out3 fb voltage adjust input; use an external voltage divider to set the output voltage 17 v out1 5 v output. voltage is internally set. 18 v out2 3.3 v output. voltage is internally set. 19 v out3 adjustable voltage output. this voltage is set through an external resistor divider. 20 vin_s3 supply rail for the standby linear regulator vout3. tie this pin to aso_rail or a separate supply rail. ep ? exposed pad of dfn device. this pad serves as the main path for thermal spreading. the exposed pad is not connected to ic ground.
ncv8614 http://onsemi.com 4 maximum ratings (voltages are with respects to gnd unless noted otherwise) rating symbol max min unit maximum dc voltage vin ? b, vin ? a, aso_rail, vbatt_mon, vin_s3, en, ignin 40 ? 0.3 v peak transient vin ? b, vin ? a, aso_rail, vbatt_mon, vin_s3, en, ignin 45 ? 0.3 v maximum dc voltage vin ? h 24 ? 0.3 v maximum dc voltage ignout, v pp , hv_det, bo_det, hot_flg, rst, dly, v out1 , v out2 7 ? 0.3 v maximum dc voltage v out3 10 ? 0.3 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. thermal information rating symbol min unit thermal characteristic (note 1) r ja 40 c/w operating junction temperature range t j ? 40 to 150 c maximum storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 1. values based on measurement of ncv8614 assembled on 2 ? layer 1 ? oz cu thickness pcb with copper area of more than 645 mm 2 with several thermal vias for improved thermal performance. refer to circuit description section for safe operating area. attributes rating symbol min unit esd capability, human body model (note 2) esd hb 2 kv esd capability, machine model (note 2) esd mm 200 v esd capability, charged device model (note 2) esd cdm 1 kv ignin esd capability, human body model (note 2) esd hb _ignin 3 kv ignin esd capability, machine model (note 2) esd mm _ignin 200 v ignin esd capability (note 3) esd_ignin 10 kv 2. this device series incorporates esd protection and is tested by the following methods: esd human body model (hbm) tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model (mm) tested per aec ? q100 ? 003 (eia/jesd22 ? a115) esd charged device model (cdm) tested per eia/jes d22/c101, field induced charge model 3. device tested with external 10 k series resistance and 1 nf storage capacitor.
ncv8614 http://onsemi.com 5 supply voltages and system specification electrical characteristics (7 v < aso_rail < 18 v, vin ? h = vin ? b aso_rail, v pp = 3.3 v, vin_s3 tied to aso_rail, vbatt_mon = 0 v, ignin = 0 v, i sys = 3 ma (note 6)) minimum/maximum values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit supply rails quiescent current (notes 4 and 6) i q t j = 25 c, i sys = 70 a, vin ? a = vin_s3 = 0 v, vin ? b = 13.2 v 34 50 a minimum operating voltage (vin ? h, vin ? b) 4.5 v thermal monitoring thermal warning (hot_flg) temperature t warn 140 150 160 c t warn hysteresis 10 20 c thermal shutdown 160 170 180 c thermal shutdown hysteresis 10 20 c delta junction temperature (tsd ? t warn ) 10 20 30 c hot_flg voltage low t j < t warn , 10 k pullup to 3.3 v 0.4 v hot_flg voltage high t j > t warn , 10 k pulldown to gnd v out2 ? 0.5 v auto switchover vin ? a quiescent current 24 a vin ? a to vin ? b risetime t j = 25 c, c aso_rail = 1 f, i sys = 400 ma 200 sec vin ? b to vin ? a falltime t j = 25 c, c aso_rail = 1 f, i sys = 400 ma 100 sec vin ? a operating threshold vin ? a rising 7.2 7.5 7.75 v vin ? a operating hysteresis vin ? a falling 100 175 250 mv max vin ? b to v aso_rail voltage drop i sys = 400 ma, vin ? b = 7 v 1.5 v max vin ? h to v aso_rail voltage drop i sys = 400 ma, vin ? h = 7.5 v 2.0 v reset (rst pin) reset threshold % of v out2 90 93 96 % hysteresis % of v out2 2.5 % reset voltage high 10 k pulldown to gnd v out2 ? 0.5 v reset voltage low 10 k pullup to 3.3 v 0.4 v delay (dly pin) charge current 2.4 5 7 a delay trip point voltage 2.0 v ignition buffer schmitt trigger rising threshold 2.75 3.25 3.75 v schmitt trigger falling threshold 0.8 1.0 1.2 v ignout voltage low ignin = 5 v, 10 k pullup to 5 v 0.4 v ignout leakage current t j = 25 c, ignout = 5 v 0.1 0.5 a vbatt monitor vbatt_mon quiescent current t j = 25 c, vbatt_mon = 13.2 v 3 5 a
ncv8614 http://onsemi.com 6 supply voltages and system specification electrical characteristics (7 v < aso_rail < 18 v, vin ? h = vin ? b aso_rail, v pp = 3.3 v, vin_s3 tied to aso_rail, vbatt_mon = 0 v, ignin = 0 v, i sys = 3 ma (note 6)) minimum/maximum values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol vbatt monitor vbatt_mon minimum operating voltage threshold where bo_det and hv_det signals become valid 1.0 2.0 2.5 v vbatt_mon hysteresis 0.25 v hv_det voltage high 10 k pulldown to gnd vbatt_mon tied to aso_rail v out2 ? 0.5 v hv_det voltage low 10 k pullup to 3.3 v vbatt_mon tied to aso_rail 0.4 v hv_det threshold vbatt_mon rising 16.2 17.8 v hv_det hysteresis vbatt_mon falling 0.2 0.35 0.5 v bo_det voltage high 10 k pulldown to gnd vbatt_mon tied to aso_rail v out2 ? 0.5 v bo_det voltage low 10 k pullup to 3.3 v vbatt_mon tied to aso_rail 0.4 v bo_det threshold vbatt_mon falling 7 7.5 8 v bo_det hysteresis vbatt_mon rising 0.2 0.35 0.5 v 4. i q is equal to i vin ? b + i vin ? h ? i sys 5. i shdn is equal to i vin ? b + i vin ? h 6. i sys is equal to i out1 + i out2 + i out3
ncv8614 http://onsemi.com 7 electrical characteristics (7 v < aso_rail < 18 v, vin ? h = vin ? b aso_rail, v pp = 3.3 v, vin_s3 tied to aso_rail, vbatt_mon = 0 v, ignin = 0 v, i sys = 3 ma (note 6)) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit low drop ? out linear regulator 1 (ldo1) specification output voltage i out1 = 0 ma to 100 ma, 7 v < aso_rail < 18 v 4.9 5 5.1 v dropout (aso_rail ? v out1 ) v dr1 i out1 = 100 ma (note 7) 500 mv load regulation i out1 = 0 ma to 100 ma, vin_b = 13.2 v 0 75 v/ma line regulation i out1 = 1 ma, 7 v < aso_rail < 18 v 0 2 mv/v output current limit 200 ma output load capacitance range co output capacitance for stability 1.0 100 f output load capacitance esr range (notes 8 and 9) esrco cap esr for stability 0.01 13 v out1 (aso low to high transient) t j = 25 c , i out1 = 100 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 10 f, vin ? a falling 70 100 mv v out1 (aso high to low transient) t j = 25 c , i out1 = 100 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 10 f, vin ? a rising 70 100 mv power supply ripple rejection (note 8) psrr vin_b = 13.2 v, 0.5 v pp , 100 hz 60 db startup overshoot i out1 = 0 ma to 100 ma 3 % low drop ? out linear regulator 2 (ldo2) specification output voltage i out2 = 0 ma to 300 ma, 7 v < aso_rail < 18 v 3.234 3.3 3.366 v dropout (aso_rail ? v out2 ) v dr2 i out2 = 300 ma (note 7) 1.5 v load regulation i out2 = 0 ma to 300 ma, vin_b = 13.2 v 0 66 v/ma line regulation i out2 = 1 ma, 7 v < aso_rail < 18 v 0 1.2 mv/v output current limit 400 ma output load capacitance range co output capacitance for stability 1.0 100 f output load capacitance esr range (notes 8 and 9) esrco maximum cap esr for stability 0.01 10 v out2 (aso low to high transient) t j = 25 c , i out2 = 300 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 22 f, vin ? a falling 30 66 mv v out2 (aso high to low transient) t j = 25 c , i out2 = 300 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 22 f, vin ? a rising 30 66 mv power supply ripple rejection (note 8) psrr vin_b = 13.2 v, 0.5 v pp , 100 hz 60 db startup overshoot i out2 = 0 ma to 300 ma 3 % low drop ? out linear regulator 3 (ldo3) specification output voltage v out3 i out3 = 0 ma to 400 ma, v out3 + v dr3 vin_s3 18 v ? 2% ? +2% v dropout (vin_s3 ? v out3 ) v dr3 i out3 = 400 ma , v out3 = 5 v (notes 7 and 10) 2.5 v output current limit 500 ma load regulation i out3 = 0 ma to 400 ma, vin_b = 13.2 v 0 75 v/ma line regulation i out3 = 1 ma, v ref vin_s3 18 v 0 654 v /v
ncv8614 http://onsemi.com 8 electrical characteristics (7 v < aso_rail < 18 v, vin ? h = vin ? b aso_rail, v pp = 3.3 v, vin_s3 tied to aso_rail, vbatt_mon = 0 v, ignin = 0 v, i sys = 3 ma (note 6)) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol low drop ? out linear regulator 3 (ldo3) specification output load capacitance range co output capacitance for stability 1.0 100 f output load capacitance esr range (notes 8 and 9) esrco maximum capacitance esr for stability 0.01 12 v out3 (aso low to high transient) t j = 25 c , i out3 = 400 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 47 f, vin ? a falling 15 36 mv v out3 (aso high to low transient) t j = 25 c , i out3 = 400 ma, i sys = 400 ma, c aso_rail = 1 f, esr co = 0.01 , co = 47 f, vin ? a rising 15 36 mv power supply ripple rejection (note 8) psrr vin_b = 13.2 v, 0.5 v pp , 100 hz 60 db startup overshoot i out3 = 0 ma to 400 ma 3 % 7. dropout voltage is measured when the output voltage has dropped 100 mv relative to the nominal value obtained with aso_rail = vin_s3 = 13.2 v. 8. not tested in production. limits are guaranteed by design. 9. refer to circuit description section for stability consideration 10. for other voltage versions refer to typical performance characteristics section. ordering information device conditions package shipping NCV8614MNR2G no enable, ldo2 reset monitor, adjustable ldo3 20 lead dfn, 5x6 (pb ? free) 2500 / tape & reel
ncv8614 http://onsemi.com 9 figure 2. automotive radio system block diagram example ncv8614 with ncv8855 34 hot_flg 38 33 sys_en ldo_en 22 21 vin hs_s hs_en 26 4 sw_fb1 8 9 7 gh1 sn1 gl1 6 5 ocset bst1 3 comp1 24 bst2 23 25 sn2 27 sw_fb2 28 comp2 37 sync 2 39 lr_g1 lr_fb1 40 isns1- 1 isns1+ 31 32 30 isns2- 29 isns2+ vin_sw smps1 vout1 smps2 vout2 ldo2 vout4 high-side switch main ldo1 vout3 smps1 power stage 8v output, 4a ilimit smps2 power stage 5v output, 2a ilimit ldo1 power stage 8.5v output, 0.4a ilimit ldo2 power stage 3.3v output, 1a ilimit am/fm tuner dvd rom drive active antenna fan headunit can usb connector main dsp vin-h vin-a vin-b 1 2 3 4 5 6 7 10 11 12 16 20 18 14 15 19 17 vbatt_mon hv_det bo_det hot_flg ignout ignin vout3 vout2 vout1 ldo1 vout1 reset / delay ldo2 vout2 ldo3 v out3 auto switchover monitoring logic ingitoin buffer 8 dly rst vin_s3 ignition filter body can main uc vpp ncv8855 ncv8614 sdars output filter 8v 8.5v 3.3v 5v 5vs 3.3vs 8v output filter output filter ldo_en hot_flg hs_en sys_en ldo_en hot_flg hs_en sys_en adj v rst dly hot_flg bo_det hv_det hot_flg_s bo_det hv_det power amplifier oring diodes & filter vbatt 8v ignition misc. 5 v logic misc. 3.3 v logic 5v 3.3v vbatt vbatt vbatt vbatt vpp 3.3vs vout3 fb vout3 fb vout3 feedback network aso_rail nc
ncv8614 http://onsemi.com 10 circuit description auto switchover circuitry the auto switchover circuit is designed to insure continuous operation of the device, automatically switching the input voltage from the aso_rail input, to the vin ? b input, to the vin ? h input depending on conditions. the primary input voltage pin is aso_rail, which is driven from the 8 v supply. when this voltage is present it will drive the output voltages. regardless of whether the 8 v supply is available, the reference and core functions of the device will be driven by the higher of vin ? b and vin ? h. the switchover control circuitry will be powered solely by the 8 v supply, via vin ? a. when the 8 v supply is not present, the gates of the 2 p ? fet switches will be pulled to ground, turning the switches on. in this condition, the vin ? b and vin ? h voltages will be diode or?ed, with the higher voltage powering the chip. the vin ? h voltage will be one diode lower than the vin ? b voltage, thereby forcing the vin ? b voltage to be dominant supply. in the event that both the 8 v supply and the vin ? b supply are not present, the vin ? h supply will be powering the device. the vin ? h supply is then fed from a recommended 1000 f cap. the duration of vin ? h supply is dependent on output current. it is intended as protection against temporary loss of battery conditions. in the event of a double battery, or prolonged high voltage condition on the battery line, a bleed transistor has been included on the vin ? h line. with the large hold ? up cap on vin ? h, the voltage on that pin has the potential to remain in an elevated position for an extended period of time. the main result of this condition would be an overvoltage shutdown of the device. in order to avoid this condition, a transistor that is connected to the overvoltage shutdown signal is tied to the vin ? h line. this transistor will become active in a high voltage event, allowing the hold ? up cap to discharge the excess voltage in a timely manner. in the block diagram, figure 1, c aso_rail is listed as a 1 f capacitor. it is required for proper operation of the device that c aso_rail is no larger than 1 f. during a switchover event, a timer in the output stages prepares the regulator in anticipation of change in input voltage. the event results in a hitch in the output waveforms, as can be seen in figure 3. figure 3. v outx response to aso switchover event i out = 100 ma c out = 47 f vin ? b/vin ? h minimum operating voltage the internal reference and core functions are powered by either the vin ? b or vin ? h supply. the higher of the two voltages will dominate and power the reference. this provides quick circuit response on start ? up, as well as a stable reference voltage. since the vin ? b voltage will come up much more quickly than the vin ? h voltage, initially, the vin ? b voltage will be running the reference. in the case of any transient drops on vin ? b, the vin ? h supply, with its large hold ? up capacitor, will then be the dominant voltage, and will be powering the reference. for proper operation of the device, vin ? b or vin ? h must be at least 4.5 v. below that voltage the reference will not operate properly, leading to incorrect functioning by the device. vin ? b or vin ? h must be greater than 4.5 v regardless of the voltage on the vin ? a pin. internal soft ? start the ncv8614 is equipped with an internal soft ? start function. this function is included to limit inrush currents and overshoot of output voltages. the soft ? start function applies to all 3 regulators. the soft ? start function kicks in for start up, start up via enable, start up after thermal shutdown, and startup after an over voltage condition. ldo3 is not subject to soft ? start under all conditions. the ldo3 output is not affected by overvoltage shutdown, and
ncv8614 http://onsemi.com 11 therefore is not effected by the soft ? start function upon the device?s return from an over voltage condition. also, when vin_s3 is connected to an independent supply and the supply is made available after the soft ? start function, ldo3 will not have an independent soft ? start. ldo1 regulator the ldo1 error amplifier compares the reference voltage to a sample of the output voltage (v out1 ) and drives the gate of an internal pfet. the reference is a bandgap design to give it a temperature ? stable output. ldo2 regulator the ldo2 error amplifier compares the reference voltage to a sample of the output voltage (v out2 ) and drives the gate of an internal pfet. the reference is a bandgap design to give it a temperature ? stable output. ldo3 regulator the ldo3 error amplifier compares the reference voltage to a sample of the output voltage (v out3 ) and drives the gate of an internal pfet. the reference is a bandgap design to give it a temperature ? stable output ldo3 is an adjustable voltage output. the adjustable voltage option requires an external resistor divider feedback network. ldo3 can be adjusted up to 10 v. the internal reference voltage is 0.996 v. to determine the proper feedback resistors, the following formula can be used: v out3 = v out3 fb [(r1+r2)/r2] figure 4. feedback network r1 r2 v outa fb v out3 stability considerations the output or compensation capacitors, c outx help determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor values and type should be based on cost, availability, size and temperature constraints. tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however, attention must be paid to esr constraints. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for each output capacitor c outx shown in figures 22 ? 27 should work for most applications; however, it is not necessarily the optimized solution. stability is guaranteed at the following values: c out1 47 f, esr 10 c out2 47 f, esr 10 c out3 47 f, esr 10 actual limits are shown in graphs in the typical performance characteristics section. thermal as power in the ncv8614 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the ncv8614 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the ncv8614 can handle is given by: p d(max) = (t j(max) ? t a )/r thja see figure 20 for r thja versus pcb area. r thja could be further decreased by using multilayer pcb and/or if air flow is taken into account. ignout circuitry the ignout pin is an open drain output schmitt t rigger, externally pulled up to 3.3 v via a 10 k resistor. the ignout pin can be used to monitor the ignition signal of the vehicle, and send a signal to mute an audio amplifier during engine crank. the ignin pin is esd protected, and can handle peak transients up to 45 v. an external diode is recommended to protect against negative voltage spikes. the ignout circuitry requires the device to be enabled for proper operation. v pp function the reset and warning circuits utilize a push ? pull output stage. the high signal is provided by v pp . v pp is tied internally to ldo2. under this setup, and any setup where ldo?s 1 ? 3 are tied to v pp , loss of the v pp signal can occur if the pull up voltage is reduced due to over current, thermal shutdown, or overvoltage conditions. reset outputs the reset output is used as the power on indicator to the microcontroller. the ncv8614 reset circuitry monitors the output on ldo2. this signal indicates when the output voltage is suitable for reliable operation. it pulls low when the output is not considered to be suitable. the reset circuitry utilizes a push pull output stage, with v pp as the high signal. in the event of the part shutting down via battery voltage or enable, the reset output will be pulled to ground. the input and output conditions that control the reset output and the relative timing are illustrated in figure 5, reset t iming. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the
ncv8614 http://onsemi.com 12 amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0 v to the delay timing threshold voltage v d of 2 v. the charging current for this is i d of 5 a. by using typical ic parameters with a 10 nf capacitor on the delay pin, the following time delay is derived: t rd = c d * v du / i d t rd = 10 nf * (2 v)/ (5 a) = 4 ms other time delays can be obtained by changing the c d capacitor value. the delay time can be reduced by decreasing the capacitance of c d . using the formula above, delay can be reduced as desired. leaving the delay pin open is not desirable as it can result in unwanted signals being coupled onto the pin. vbatt_mon and warning flags the ncv8614 is equipped with high voltage detection, brown out detection, and high temperature detection circuitry. the overvoltage shutdown, high voltage, and brown out detection circuitry are all run off the vbatt_mon input. if this functionality is not desired, grounding of the vbatt_mon pin will turn off the functions. the hv_det and bo_det signals are in a high impedance state until the vba tt_mon circuitry reaches it minimum operating voltage, typically 1.0 v to 2.5 v. at that point the bo_det signal will be held low, while the hv_det signal will go high. the bo_det signal will go high once the vbatt_mon signal reaches the brown out threshold, typically 7 v to 8 v. the bo_det signal will stay high until the vbatt_mon voltage drops below the brown out threshold. the hv_det signal will stay high until the vbatt_mon voltage rises above the hv_det threshold, typically 16.2 v to 17.8 v. the hv_det signal will reassert high once the hv_det signal crosses the hv_det threshold going low. the ncv8614 is also equipped with a hot flag pin which indicates when the junction temperature is approaching thermal shutdown. the hot flag signal will remain high as long as the junction temperature is below the hot flag threshold, typically 140 c to 160 c. this pin is intended as a warning that the junction temperature is approaching the thermal shutdown threshold, which is typically 160 c to 180 c. the hot flag signal will remain low until the junction temperature drops below the hot flag threshold. the hot_flag circuitry does not run off the vbatt_mon pin, and can not be disabled by grounding vbatt_mon. each of the three warning circuits utilizes a push ? pull output stage. the high signal is provided by v pp . v pp is internally tied to v out2 . overvoltage shutdown the ncv8614 is equipped with overvoltage shutdown (ovs) functionality. the ovs is designed to turn on when the vbatt_mon signal crosses 17 v. if the vbatt_mon pin is tied to ground, the ovs functionality will be disabled. when ovs is triggered, ldo1 and ldo2 will both be shut down. ldo3 is run off a separate input voltage line, vin_s3, and will not shutdown in this condition. once the ovs condition has passed, ldo1 and ldo2 will both turn back on. the vin ? h line is equipped with a bleed transistor to prevent a continued ovs condition on the chip once the high battery condition has subsided. this transistor is needed to discharge the high voltage from the vin ? h hold ? up capacitor. this transistor will only turn on when an ovs is detected on ? chip, and will turn off as soon as the ovs condition is no longer detected by the chip.
ncv8614 http://onsemi.com 13 figure 5. ncv8614 reset timing diagram vin ldox delay reset load dump 17 v power on reset overload on output over voltage on input momentary glitch on output shutdown via input vout reset threshold overvoltage on input figure 6. ignout timing diagram 4.4 v 7.0 v < 1 v 5.0 v load dump vin_b ignin ignout 45 v > 3.25 v ? 100 v
ncv8614 http://onsemi.com 14 figure 7. auto switchover circuit timing diagram vbattmon connected to aso_rail voltage clamped at 16 v t vin ? h d vin ? h duration of t vin ? h and drop of d vin ? h dependant on output load conditions 8v vin_a 17v 13.2v vin_b 16v 13.2v vin_h xxv 17v 13.2v 7v aso_rail ldox delay reset 8v switching output voltage from smps asic turns on. 8v switching output voltage from smps asic turns off. loss of vin ? b undervoltage lockout vin ? b turns back on overvoltage shutdown 8v switching output voltage from smps asic turns on. shutdown
ncv8614 http://onsemi.com 15 figure 8. warning circuitry timing diagram 17v 16.5v vbatt_mon 8v 7.85v 7.5v 2.5v 1.5v vpp hv_det vpp bo_det overvoltage on input voltage dip on input 2.0v 1.0v figure 9. thermal shutdown timing diagram 170 c 160 c 150 c 140 c ldox t j v pp hot_flg hot flag triggers thermal shutdown thermal recovery hot flag recovers
ncv8614 http://onsemi.com 16 figure 10. ncv8614 regulator output timing diagram? vin_s3 tied to aso_rail 19v 13.2v 7v 5.0v 3.3v aso_rail vin_s3 ldo1 ldo2 ldo3 delay reset ldo2 reset threshold overvoltage shutdown glitch on ldo2
ncv8614 http://onsemi.com 17 figure 11. ncv8614 regulator output timing diagram ? vbatt_mon grounded 17v 13.2v 13.2v aso_rail ldo1 ldo2 ldo3 load dump
ncv8614 http://onsemi.com 18 4.9 4.92 4.94 4.96 4.98 5.0 5.02 5.04 5.06 5.08 5.10 ? 40 ? 20 0 20 40 60 80 100 120 140 v out1 , output voltage (v) temperature ( c) figure 12. output voltage ldo1 vs temperature i out1 = 100 a ? 40 ? 20 0 20 40 60 80 100 120 140 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 temperature ( c) figure 13. output voltage ldo2 vs temperature v out2 , output voltage (v) i out2 = 100 a 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 ? 40 ? 20 0 20 40 60 80 100 120 140 v out3 , output voltage (v) temperature ( c) figure 14. output voltage ldo3 vs temperature i out3 = 100 a 0 50 100 150 200 250 0 20 40 60 80 100 v dr1 , dropout voltage (mv) i out1 , output current (ma) figure 15. dropout ldo1 vs output current t j = 25 c v out1 = 5.0 v v dr2 , dropout voltage (mv) i out2 , output current (ma) figure 16. dropout ldo2 vs output current t j = 25 c v out2 = 3.3 v 0 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300 350 40 v dr3 , dropout voltage (mv) i out3 , output current (ma) figure 17. dropout ldo3 vs output current t j = 25 c v out3 = 5.0 v 0 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300
ncv8614 http://onsemi.com 19 16.5 17 17.5 18 18.5 19 19.5 1 10 100 1000 10000 100000 1000000 hv_det threshold (v) aso ? rail voltage ramp (v/s) figure 18. hv ? det threshold vs. dv/dt figure 19. ldo3 dropout voltage vs. output voltage figure 20. r ja vs. copper area figure 21. r ja vs. duty cycle 30 50 70 90 110 130 170 0 100 200 300 400 500 700 pcb copper area (mm 2 ) r ja , thermal resistance junction ? to ? ambient ( c/w) 150 600 1 ? oz cu single layer pcb 0 0.5 1 1.5 2 2.5 3.5 10 12345 7 v out3 , output voltage (v) v dr3 , dropout voltage (v) 3 6 t = 25 c i out3 = 400 ma 89 0.001 0.01 0.1 1 10 100 1000 1e ? 06 1e ? 05 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) r ja , ( c/w) single pulse tsp d = 0.5 0.2 0.1 0.05 0.01 2 ? oz cu single layer pcb, 100 mm 2 2 ? oz cu single layer pcb
ncv8614 http://onsemi.com 20 0.001 0.01 0.1 1 10 100 0 20406080100 esr ( ) i out1 , output current (ma) figure 22. c out1 esr stability region ? 1 f v in = 18 v v out1 = 5 v c out1 = 1 f stable region unstable region i out2 , output current (ma) figure 23. c out1 esr stability region ? 47 f v in = 18 v v out2 = 3.3 v c out2 = 1 f 0 50 100 150 200 250 300 i out3 , output current (ma) figure 24. c out2 esr stability region ? 1 f v in = 18 v v out3 = 1.0 v c out3 = 1 f figure 25. c out2 esr stability region ? 47 f figure 26. c out3 esr stability region ? 1 f figure 27. c out3 esr stability region ? 47 f unexplored region* *the min specified esr is based on murata?s capacitor grm31cr60j476me19 used in measurement. the true min esr limit might be lower than shown. 0.001 0.01 0.1 1 10 100 0 20406080100 esr ( ) i out1 , output current (ma) v in = 18 v v out1 = 5 v c out1 = 47 f stable region unstable region unexplored region* 0.001 0.01 0.1 1 10 100 0 50 100 150 200 300 esr ( ) stable region unstable region 250 i out2 , output current (ma) v in = 18 v v out2 = 3.3 v c out2 = 47 f 0.001 0.01 0.1 1 10 100 0 50 100 150 200 300 esr ( ) stable region unstable region unexplored region* 250 0.001 0.01 0.1 1 10 100 esr ( ) stable region unstable region 350 400 0 50 100 150 200 250 300 i out3 , output current (ma) v in = 18 v v out3 = 1.0 v c out3 = 47 f 0.001 0.01 0.1 1 10 1000 esr ( ) stable region unstable region 350 400 100 unstable region *the min specified esr is based on murata?s capacitor grm31cr60j476me19 used in measurement. the true min esr limit might be lower than shown.
ncv8614 http://onsemi.com 21 figure 28. output response of ldo3 to loss of vin ? b i out3 = 400 ma dt = 20.6 ms figure 29. output response of ldo2 to loss of vin ? b i out2 = 80 ma dt = 121 ms
ncv8614 http://onsemi.com 22 figure 30. hv ? det response to high voltage ? vbat ? mon tied to aso ? rail figure 31. hv ? det response to high voltage ? vbat ? mon left open
ncv8614 http://onsemi.com 23 figure 32. bo ? det response to low voltage ? vbat ? mon tied to aso ? rail figure 33. bo ? det response to low voltage ? vbat ? mon left open
ncv8614 http://onsemi.com 24 figure 34. output response to ovs ? vbat ? mon tied to aso ? rail figure 35. output response to ovs ? vbat ? mon left open
ncv8614 http://onsemi.com 25 package dimensions dfn20 case 505ab ? 01 issue b c 0.15 e2 d2 l b 20x a d notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to plated terminals and is measured between 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. e c e a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.65 0.75 a3 0.20 ref b 0.20 0.30 d 6.00 bsc d2 3.98 4.28 e 5.00 bsc e2 2.98 3.28 e 0.50 bsc k 0.20 ??? l 0.50 0.60 c 0.15 pin 1 location a1 (a3) seating plane c 0.08 c 0.10 a2 20x k 20x a 0.10 b c 0.05 c note 3 110 11 20 2x 2x top view side view bottom view *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 dimensions: millimeters 0.78 20x 4.24 3.24 5.30 0.35 20x 0.50 pitch package outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8614/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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